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Heterostructure Negative Differential Resistance Device


Stanford Reference:

06-086


Abstract


Researchers in Prof. James Plummer's laboratory have developed a patented silicon-compatible negative differential resistance (NDR) device with high peak to valley current ratios (PVCR's). This invention is based on SiGe gated tunneling diodes and is arranged for selective passage of current through relatively high tunneling efficiency regions and relatively low tunneling efficiency regions. This design has excellent scalability since a minimum sized structure can now be inserted into a DRAM (dynamic random access memory) cell.

Applications


  • Semiconductors
    • memory
    • microprocessors
    • ASIC

Advantages


  • Large peak currents and very high PVCR - as high as 295 at room temperature/1113 at -65oC
  • Excellent scalability - because the peak current comes from tunneling and does not scale with channel length
  • CMOS-compatible - the process is silicon-compatible, with no III-V materials, so it can easily be integrated into conventional CMOS technology
  • Robust and high yield process

Publications



Innovators & Portfolio



Patent Status



Date Released

 7/17/2013
 

Licensing Contact


Anne Kopf-Sill, Licensing Associate
(650)498-8015 (Business)
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Related Keywords


semiconductor: ASIC and ASSP   SiGe   06-086   Germanium   SRAM   semiconductor: memory   memory   Integrated circuits   DRAM   computer memory   semiconductors   
 

   

  

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