During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing techniques are costly due to ad hoc, manual methods.
Stanford researchers have developed new Fast Quick Error Detection (Fast QED) tests that are four orders of magnitude faster than standard QED tests while also preserving quick error detection properties.
Researchers at Stanford have demonstrated a new type of energy-efficient and ultrathin memory. This low-energy cost memory is based on stacking orders in the atomically thin limit, associated with tiny changes in the position of one atomic layer with respect to another.
This patented technology is a scalable, reliable non-volatile memory device that uses graphene as a thermal barrier to improve energy efficiency and reliability of phase change material (PCM).