S13-406 Post-Silicon Validation for Complex SoCs with Accelerators Stanford researchers have designed a systematic technique for post-silicon validation in system-on-chips (SoCs). Keith Campbell Hai Lin Deming Chen Subhasish Mitra
S15-110 Symbolic Quick Error Detection (Symbolic QED) During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing techniques are costly due to ad hoc, manual methods. Subhasish Mitra Clark Barrett Eshan Singh Hai Lin