Researchers in the Murmann Mixed Signal Group have developed a pipelined chip architecture with inverted residual and linear bottlenecks-based networks for energy efficient Machine Learning inference on edge devices.
During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing techniques are costly due to ad hoc, manual methods.
Stanford researchers have developed new Fast Quick Error Detection (Fast QED) tests that are four orders of magnitude faster than standard QED tests while also preserving quick error detection properties.