Docket #: S07-039
Flattened Butterfly : Cost-efficient High-Radix Topology
Researchers in Prof. William Dally's laboratory have developed a novel, cost-efficient topology for high-radix networks. This technology uses concentrated high-radix routers and a globally load-balancing routing algorithm to decrease the number of links (or cables) in high-performance interconnection networks such as supercomputer or data centers. The flattened butterfly requires half as many cables as folded-Clos topology with better path diversity than a conventional butterfly.
Ongoing Research
The inventors continue their research on the flattened butterfly to better understand implementation issues.
Related Technolgies from The Dally Lab:
Stanford Docket S14-246 "Probabilistic Cache Replacement to Reduce Cache Misses"
Stanford Docket S11-305 "Speculative Reservation Protocol"
Stanford Docket S12-138 "High-Radix Interprocessor Communications System and Method"
Stanford Docket S07-359 "Technology-Driven, Highly-Scalable Dragonfly Topology"
Applications
- High performance interconnection networks, such as:
- multiprocessor computer systems
- data communication networks
Advantages
- Low cost - reduces the number of cables by approximately 2x, compared to a high-radix folded-Clos topology (therefore the folded butterfly is roughly half the cost of a comparable performance Clos network)
- High performance - can lead to an order of magnitude increase in performance compared to a conventional butterfly
Publications
- John Kim, William Dally, Dennis Abts "Flattened Butterfly : A Cost-efficient Topology for High-Radix Networks" Proceedings of the 34th International Symposium on Computer Architecture (ISCA-34) San Diego, California, June 2007.
- U.S. Patent Application: "Flattened Butterfly Processor Interconnect Network" (Publication No. 20090106529)
Patents
- Published Application: 20090106529
- Issued: 8,285,789 (USA)
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High-Radix Interprocessor Communications System and Method S12-138High-Radix Interprocessor Communications System and Method
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