Symbolic Quick Error Detection (Symbolic QED)

During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing techniques are costly due to ad hoc, manual methods. Such techniques become increasingly difficult to apply as ICs become increasingly complex. For example, traditional post-silicon validation and debug techniques may take days, weeks, even months of manual effort per bug.

Stanford and NYU researchers have addressed this challenge with a structured approach to post-silicon logic bug localization and debug. This technique is systematic and completely automated. As a result, this invention can significantly reduce the costs of post-silicon validation and debug. The technique can also be used to localize logic bugs during pre-silicon verification as well as emulation-based verification.

Stage of Research:

(as of Sept 2015)

Additional, complimentary QED Post-Silicon Validation technologies: