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A Novel Heterostructure FET with High On Current and Low Leakage


Stanford Reference:

06-093


Abstract


Engineers in Prof. Krishna Saraswat’s laboratory have developed and patented a heterostructure technology for semiconductor devices exhibiting high channel mobility and low leakage including CMOS-compatible semiconductor devices and MOSFETs. This structure dramatically reduces (100X) band-to-band tunneling (BTBT) leakage currents while maintaining very high drive currents. The technology can be applied to a range of high-mobility materials (such as Ge, InSb, InAs, and strained Ge or SiGe). These heterostructures will allow FET (field effect transistor) scaling down to the sub 15 nm range.

Applications


  • Semiconductors – MOSFETs and other devices

Advantages


  • CMOS compatible
  • Low BTB leakage
  • High drive currents

Publications



Acknowledgement


This work was supported by the Microelectronics Advanced Research Corporation (MARCO).

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Patent Status



Date Released

 12/2/2014
 

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Related Keywords


Field effect transistors   non volatile memory device   semiconductors   semiconductor: memory   compound semiconductor   Germanium   high performance computing   MOSFET   nanostructure   semiconductor: chip architecture   SiGe   VLSI   CMOS   integrated circuits   
 

   

  

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