High Fidelity, Radiation Tolerant Analog-to-Digital Converter

Stanford researchers have patented a radiation-tolerant, pipeline analog-to-digital converter (ADC) in a fully commercial CMOS technology. A novel digital self-calibration algorithm is used to achieve wideband high fidelity (90-dB SFDR) at low power (60 mW) and megahertz sampling rates (5 MS/s), and radiation-hardness-by-design techniques are used to overcome radiation damage effects such as transistor parameter shifts, increased transistor leakage current, and single event effects (e.g., charge accumulation, latchup). The stated performance is sustained through a total dose of 1 Mrad(Si) and the converter displays no latchup up to an LET of at least 63 MeV-cm2/mg (highest tested LET) at elevated temperature (130 degrees C) and supply. While demonstrated in a 0.25-um bulk CMOS process (single-well, STI interdevice isolation, non-epitaxial substrate), both the self-calibration algorithm and the radiation-hardness by design techniques can be readily applied to other manufacturing processes to achieve robust, high-fidelity, wideband analog-to-digital conversion.