Researchers in the Murmann Mixed Signal Group have developed a pipelined chip architecture with inverted residual and linear bottlenecks-based networks for energy efficient Machine Learning inference on edge devices.
Engineers in Prof. Krishna Saraswat's laboratory have developed a scalable 1-transistor (1T) dynamic random access memory (DRAM) with a gallium phosphide (GaP) source-drain on silicon.
Researchers in Stanford's Nanoscale Prototyping Laboratory have developed a low-temperature process for fabricating etch-resistant, pinhole-free spacer dielectrics a few nanometers thick.
Researchers in Prof. James Plummer's laboratory have developed a patented silicon-compatible negative differential resistance (NDR) device with high peak to valley current ratios (PVCR's).