Heterostructure 1-Transistor DRAM with Improved Retention Time

Engineers in Prof. Krishna Saraswat's laboratory have developed a scalable 1-transistor (1T) dynamic random access memory (DRAM) with a gallium phosphide (GaP) source-drain on silicon. Because a 1T DRAM does not have a capacitor (compared to conventional 1-transistor 1-capacitor DRAM), they can achieve higher device density and are more compatible with CMOS embedded memory applications. This technology then takes advantage of GaP's high bandgap (2.26eV) to overcome retention time issues that have been problematic for traditional 1T DRAM. Finally, the device can be made in the FinFET structure, enabling better scalability than conventional planar silicon 1T DRAM. This 1T DRAM could be used for either stand-alone or embedded memory applications.