Heterostructure transistors with high hole and electron mobility

Engineers in Prof. Krishna Saraswat's laboratory have developed a patented heterostructure channel transistor based on III-V semiconductor materials and designed for optimum hole transport. Using III-V materials (such as antimony) enables continued scaling of transistor performance beyond what can be achieved with standard silicon. This high mobility channel design addresses problems related to interfaces between materials and confinement of both holes and electrons. The inventors have also demonstrated a heterostructure design with high offsets for confining both electrons and holes in the high mobility channel. These transistors are well suited for end user applications in high frequency (THz range) and analog applications.