We present a revolutionary advancement in ferroelectric materials that is set to redefine the landscape of embedded memories and semiconductor technologies.
Researchers in the Robust Systems Group at Stanford University developed a method for dividing the available resistance window in a multi-bit per cell Resistive RAM into varying resistance distributions to improve read and program performance.
Engineers in Prof. H.-S. Philip Wong's laboratory have developed a lower power, three-dimensional resistive random access memory (RRAM) device using an atomically thin graphene edge electrode.
Engineers in Prof. Krishna Saraswat's laboratory have developed a scalable 1-transistor (1T) dynamic random access memory (DRAM) with a gallium phosphide (GaP) source-drain on silicon.