During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing techniques are costly due to ad hoc, manual methods.
Researchers in the Stanford University Power Electronics Research Lab have designed an easy to implement, high-efficiency, high-frequency power amplifier with low voltage stress.
Researchers at Stanford have developed a method to tune power amplifier circuits to directly connect their output power (and adjust the combined output power) without any additional power combiner network.
Stanford researchers have developed a damage free method for activating buried p-type or Mg-doped epitaxial layers in III-nitride devices that improves performance and can reduce device cost when used as edge termination.
Stanford researchers have designed a high-voltage cascode GaN/SiC device combining the advantages of both a GaN and an SiC device (i.e. reduced gate loss/simple gate drive requirements)
Engineers in Prof. Zhenan Bao's laboratory have developed a fully elastic, highly stretchable fluorinated polymer that can be used as a photoresist with standard lithography techniques for precise patterning of flexible electronic devices.
Stanford researchers have patented a fabrication process for monolithic integration of different epitaxial materials on the same substrate for improved coupling of optoelectronic devices.
Stanford researchers patented a method to design, computationally optimize and fabricate efficient optical devices using semiconducting and dielectric nanostructures.
Researchers in Profs. Jonathan Fan and Jim Plummer's laboratory have patented a generalized, CMOS-compatible process to fabricate single crystal metal components on amorphous insulator substrates.
Stanford researchers at the Cui Lab have designed a self-aligned hybrid metal-dielectric surface that offers unparalleled performance in applications where both a transparent contact and a photon management texture are needed.
Researchers in Stanford's Nanoscale Prototyping Laboratory have developed a low-temperature process for fabricating etch-resistant, pinhole-free spacer dielectrics a few nanometers thick.