Researchers in the Murmann Mixed Signal Group have developed a pipelined chip architecture with inverted residual and linear bottlenecks-based networks for energy efficient Machine Learning inference on edge devices.
Stanford researchers have developed new Fast Quick Error Detection (Fast QED) tests that are four orders of magnitude faster than standard QED tests while also preserving quick error detection properties.
Stanford researchers have developed new Fast Quick Error Detection (Fast QED) tests that are four orders of magnitude faster than standard QED tests while also preserving quick error detection properties.
During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing techniques are costly due to ad hoc, manual methods.
Researchers at Stanford have developed a simpler and low-cost micro-cavity design for color tuning of organic light emitting devices (OLEDs) for display applications. A micro-cavity is an essential part of OLED display for high color purity.
This invention is a set of structures and associated processes to integrate GaN with Diamond to develop a full complementary CMOS device capable of operation in high power and high temperature applications.
Stanford researchers have designed a high-voltage cascode GaN/SiC device combining the advantages of both a GaN and an SiC device (i.e. reduced gate loss/simple gate drive requirements)
Magnetic field measurements using currently available devices require complex switching circuitry to mitigate the offset and noise present in measurements.
Stanford researchers have designed a frequency-multiplexed neural probe architecture that enables massive scaling of electrophysiological recording from neurons.
Stanford researchers have patented an image sensor that overcomes frame rate and power consumption limits for high-speed mega-pixel imaging, and therefore can extend battery life for mobile phone cameras.
Stanford researchers have developed a new technology to create a programmable yet low power processing core targeting imaging systems. This core is built around a 2D-stencil processing data-path.